Mike Ekberg firstname.lastname@example.org 415-863-1716(h)
RLO CONSULTING,INC. http://rloc.biz 650-380-6065(c)
1727 Page St.
San Francisco, CA 94117
U.S. Pat. 5,977,001. B.S. California State University, Chico, Computer Science,
M.A. American University
Seeking contract position in application, systems, or web/tool development or management.
1997 – present PRESIDENT AND CTO/CONSULTANT, RLOC CONSULTING, INC.
RLO Consulting specializes in developing large scale highly parallel
verification environments that are individually tailored to our client's
needs. Wide experience in:
- Task automation via Perl/makefile/SCM scripting
- Web design tools
- Database design, implementation
- Open source tools and development
- Perl/C/C++ programming
- Linux/Unix expert
- Installation, enhancement, automation and maintenance
of SW configuration management tools
Representative projects :
April 2009 – present
Design and development of package of legal discovery tools to
automatically extract information from disk drives and provide
access to litigators using a custom designed website and tool set
using Perl, PHP, MySQL and various open source tools, running on
a LAMP/Ubuntu web server.
January 2006 – April 2009 Verification Support for Microsoft XBOX
Responsible for porting Verilog/C++ Xbox graphics Linux-based
64-bit verification environment from GNU GCC 2.9.5 to GCC 3.3.5.
Verification environment has 100,000+ files, including 30,000+
test cases in C++. RTDA Flowtracer SW for parallel job
submission on 100+ Opteron Linux CPUs. Enhanced Makefile/Perforce
SCM build system. Created build/release protocol to synchronize
chip and test environment between Microsoft and IBM development
teams, using Perforce and Perl scripts.
April 2001 – January, 2002 Verification and Customer Support for iReady Corporation
ASIC verification and prototype creation. Ran regressions,
released netlists, ran design tools.
Apr 2001 – Sep 2001 Verification for Microsoft Corporation’s WebTV Division
Verification of 3D graphic’s portion of next-generation Ultimate
TV set top box. Testing of Verilog simulation of ASIC Hardware.
Enhanced simulation/regression environment. Covermeter coverage
Sr. Verification Engineer/Manager/Director, iReady Corporation
Verification engineer/manager/director for a small Internet
startup designing and testing hardware implementation of a
network stack using TCP/IP/PPP/Ethernet protocols.
Sr. Manager, Verification, Silicon Graphics, Inc.
Verification manager for very large workstation graphics
accelerator project of 100+ engineers.
Simulation Lead, NVIDIA, Inc.
Design and development of multiple stream, Verilog and
C-based graphics verification environment.
Senior Product Development Engineer, Cirrus Logic, Inc.
Wrote a clock-cycle accurate C++ simulator for Windows
accelerator display pipeline.
Hardware Manager 1, Sun Microsystems, Inc.
Managed the design, development and verification of several
successful graphics hardware accelerators.
Additional Contact information is available on the Information Page.
Software Contractors' Guild (www.scguild.com)
Copyright(c) 1995 - 2000 Mike Ekberg and Software Contractors' Guild,
Post Office Box 257,Nottingham, NH USA 03290-0257